1. Field of the Invention
The invention generally relates to a manufacturing process for integrated circuits, and more particularly, relates to a method for fabricating MOS (metal-oxide-semiconductor) devices having gate oxide layers of different thicknesses for diverse uses.
2. Description of the Related Art
As the size of integrated circuit devices, especially their channel lengths, are scaled down to the range of sub-half micro dimensions, the gate oxide layer of MOS devices will approach the thickness range of several tens of Angstroms. 3.3 V or even smaller supply voltages will be gradually accepted where high density VLSI circuits are required, since there are reliability issues when operating a sub-half micro MOSFET at 5 V. However, although such a 3.3 V operating voltage is compatible with the sub-half micro device for its core circuit to ensure good device reliability, there is still a need for a 5 V supply voltage to provide compatibility with other systems. For example, MOS devices used in periphery circuits, such as power-down circuits and a portion of I/O protection circuits, are typically operated at 5 V supply voltage. These MOS devices are provided with a longer channel length and a thicker gate oxide layer than that used in the core circuit because of operational speed requirements. Therefore, employing these type of combined VLSI circuits necessitates a technique for fabricating gate oxide layers of different thicknesses for diverse uses within the same silicon substrate. In addition, the fabrication technique to produce gate oxide layers with different thicknesses would be applicable to devices which require two different threshold voltages, such as read only memory (ROM) devices.
A conventional method for fabricating gate oxide layers of different thicknesses is depicted in FIGS. 1A-1D, which illustrate the process flow in cross-sectional views. First referring to FIG. 1A, there is shown monocrystalline silicon substrate 1. While field oxide layer 10 is formed on the predetermined region of silicon substrate 1 to define a plurality of first active regions and second active regions therebetween, FIG. 1A shows just two active regions, namely first active region 11 and second active region 12, respectively. A thermal oxidation process is applied to the surface of first active region 11 and second active region 12 to form oxide layer 13 thereon. This oxidation process is performed within the temperature range of 750.degree.-1000.degree. C. for 10 minutes to 2 hours.
By photolithography technique, photoresist layer 100 is formed onto a portion of oxide layer 13 to shield second active region 12. The portion of oxide layer 13 within first active region 11 is then etched by hydrofluoric acid using the photoresist layer as masking to remove the portion of oxide layer 13 in active region 11, as depicted in FIG. 1B. After removing the photoresist layer with sulfuric acid, silicon substrate 1 is subjected to a thermal oxidation process to grow first gate oxide layer 14 over first active region 11 and second gate oxide layer 15 over the second active region, respectively. In particular, second gate oxide layer 15 is formed by incorporating the portion of oxide layer 13 of second active region 12. Because second gate oxide layer 15 is formed by oxidizing twice, the thickness of second gate oxide layer 15 is larger than that of first gate oxide layer 14, as FIG. 1C illustrates. Referring to FIG. 1D, gate electrodes 16 are defined by the steps, sequentially, of depositing a polysilicon layer, patterning and etching the polysilicon layer. Impurities are implanted into silicon substrate 1 to form source/drain regions 17 using gate electrodes 16 as masking. MOS devices having gate oxide layers of different thicknesses are thereby attained.
However, in the conventional method, it is necessary that photoresist layer 100 be removed prior to the oxidation process for growing first gate oxide layer 14 and second oxide layer 15. As a result, during the removal process underlying oxide layer 13 is subject to contamination. For example, the method employed in removing the photoresist layer makes use of a chemical solution and even more oxygen plasma for eradicating it exactly. During this aspect of the process, the oxygen plasma can pollute oxide layer 13. This can result in a deterioration in oxide layer dielectric characteristics and reliability when oxide layer 13 is later incorporated into second gate oxide layer 15. Furthermore, it is difficult to control the oxidation speed of gate oxide layer 15 as it merges together with oxide layer 13. This indirectly affects the accuracy of gate oxide thickness.